APPLIED PHYSICS LETTERS 95, 222905 ͑2009͒
Aixia Lu, Jia Sun, Jie Jiang, and Qing Wana͒
Key Laboratory for Micro-Nano Optoelectronic Devices of Ministry of Education and State Key Laboratory of
Chemo/Biosensing and Chemometrics, Hunan University, Changsha 410082, People’s Republic of China
͑Received 18 September 2009; accepted 6 November 2009; published online 4 December 2009͒
Electric-double-layer ͑EDL͒ effect is observed in microporous SiO2 dielectric films deposited at
room temperature by plasma-enhanced chemical vapor deposition method. Indium tin oxide
thin-film transistors gated by such microporous SiO2 gate dielectric are fabricated at room
temperature, and a low operating voltage of 1.5 V is obtained due to the huge EDL specific
capacitance ͑2.14 F/cm2͒. The field-effect electron mobility is estimated to be 118 cm2 V−1 s−1.
Current on/off ratio and subthreshold gate voltage swing are estimated to be 5ϫ106 and 92 mV/
decade, respectively. Room-temperature deposited microporous SiO2 dielectric is promising for
low-power field-effect transistors on temperature sensitive substrates. © 2009 American Institute of
In field-effect thin-film transistors ͑TFTs͒, the semicon-
ductor channel is insulated from the gate electrode by a di-
electric layer, and the gate/dielectric stack is responsible for
inducing mobile charges in the active channel.1 While exten-
sive consideration has been given to new semiconducting
channels with respect to understanding and improving
of intense current interest for many reasons, particularly for
low power application and portable electronics.4,5 In general
terms, the performance of TFTs can be improved by using
gate dielectric with higher specific capacitance.6 The benefits
of higher specific capacitance are ͑1͒ much higher output
current at a given applied gate voltage and ͑2͒ much lower
operating voltages; both are a direct consequence of the large
two-dimensional electron density that can be induced in the
channel by means of the high specific capacitance.
In order to get higher specific capacitance for low-
voltage operation, thinner SiO2 and insulators with high di-
ample, the operating voltage of InGaZnO4 TFTs gated with
amorphous BaSrTiO3 was reduced down to 3.0 V.11 Another
interesting approach to achieve low-voltage operation is us-
ample, low-voltage organic transistors gated by ionic liquids
SiO2 with EDL effect was deposited by plasma-enhanced
chemical vapor deposition ͑PECVD͒ method at room tem-
perature. The room-temperature processed indium tin oxide
͑ITO͒ TFTs gated by such microporous SiO2 dielectric
showed a low operating voltage of 1.5 V due to the high
specific capacitance ͑2.14 F/cm2͒. The mobility, current
on/off ratio, and subthreshold swing were estimated to be
118 cm2/V s, 5ϫ106, and 92 mV/decade, respectively.
Microporous SiO2 films with the thickness of about
8.0 m were deposited on n+-type Si ͑100͒ substrates by
PECVD using SiH4 and O2 as reactive gases at room tem-
perature. The flow rate ratio of SiH4/O2 was 5:18 SCCM
͑SCCM denotes standard cubic centimeter per minute at
STP͒. The deposition pressure and deposition time were 25
Pa and 1 h, respectively. Coplanar homojunction TFTs with
ITO channel layer were fabricated and characterized. First,
50-nm-thick ITO channel layers were deposited on the mi-
croporous SiO2 dielectric by radio frequency ͑rf͒ magnetron
sputtering in Ar/O2 mixed ambient at 0.5 Pa. Then, highly
conductive ITO source and drain electrodes with the thick-
ness of 100 nm were deposited by rf magnetron sputtering
and patterned using a nickel shadow masks in pure argon
ambient at 0.5 Pa. The channel length and width-to-length
ratio of the TFTs were 80 m and 5:1, respectively. The
entire process of device fabrication was performed at room
temperature. The structural characterization of the mi-
croporous SiO2 was investigated by field emission scanning
electron microscopy ͑Hitachi S-4800 SEM͒. The electrical
characterizations of the microporous SiO2 dielectric and
ITO-based TFTs were investigated by an impedance analyzer
͑Agilent 4292A͒ and a semiconductor parameter analyzer
͑Keithley 4200 SCS͒ at room temperature.
Figure 1͑a͒ shows a cross-section SEM image of the
as-deposited SiO2 film, and its thickness is found to be
ϳ8.0 m. The inset in Fig. 1͑a͒ shows a high-resolution
SEM image of the SiO2 dielectric. A microporous structure
with high-density nanoclusters is clearly observed. A mi-
croporous material is a material containing pores with
diameters less than 2.0 nm.15 The capacitance-frequency
͑C-f͒ curve in 40 Hz–10 kHz range is presented in Fig. 1͑b͒.
The inset of Fig. 1͑b͒ is the schematic diagram of
ITO/SiO2/n+-Si sandwich structure for capacitance mea-
surement. Although the physical thickness of the mi-
croporous SiO2 was 8.0 m, the measured specific capaci-
tance is as large as 2.14 F/cm2 at 40 Hz. It was also found
that it decreased with increasing frequency and reduced to
16.6 nF/cm2 at 10 kHz. The relationship between the ca-
pacitance and frequency is in good agreement with that of
the ion gels or SiO2 deposited by PECVD using SiH4 and O2
as reactive gas.12,16 The main contributions to the capaci-
tance at low frequencies are interpreted to be the response of
a͒
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95, 222905-1
© 2009 American Institute of Physics
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